One technique that is used in semiconductor manufacture for planarizing dielectric layers is chemical mechanical polishing (planarizing) or (CMP). Chemical mechanical polishing involves holding and rotating a semiconductor wafer against a wetted polishing platen under controlled chemical, pressure and temperature conditions. Typically an aqueous colloidal silica solution is used as the abrasive fluid. The polishing mechanism is a combination of mechanical action and the chemical reaction of the material being polished with the aqueous solution.
As circuit densities increase, chemical mechanical polishing has become one of the most viable techniques for planarization particularly for interlevel dielectric layers. In view of this, improved methods of chemical mechanical polishing are being increasingly sought. One aspect of chemical mechanical polishing in need of improvement is the speed and throughput of the process for semiconductor manufacture. In general, CMP is a relatively slow and time consuming process. During the polishing process semiconductor wafers must be individually loaded into a carrier, polished and then unloaded from the carrier. The polishing step in particular is very time consuming and may require several minutes.
Recently, different techniques have been used in the art for increasing the speed and throughput of the CMP process. As an example, more aggressive aqueous solutions have been developed to increase the speed of the polishing step. Higher carrier downforces and higher rpms for the polishing platen are also sometimes used. Although these techniques are somewhat successful, they may adversely effect the polishing process and the uniformity of the polished surface.
Endpoint detection, for instance, is more difficult to control when aggressive solutions and higher carrier downforces are employed. In addition, the polishing process may not proceed uniformly across the surface of the wafer. The hardness or composition of a dielectric layer (or polishing platen) may vary in certain areas. This in turn may cause a dielectric layer to polish faster or slower in some areas effecting its global planarity. This problem may be compounded by aggressive solutions, higher carrier downforces and increased rpms.
In view of these and other problems of prior art CMP processes, there is a need in the art for improved methods of CMP. In addition, there is a need in the art for improved methods of forming and planarizing dielectric layers. Accordingly, it is an object of the present invention to provide an improved method of CMP and an improved method of forming and planarizing dielectric layers using CMP. It is a further object of the present invention to provide an improved method of CMP that is suitable for large scale semiconductor manufacture and in which increased process speeds and throughput are obtained without sacrificing global planarity. It is a further object of the present invention to provide an improved method of forming and planarizing dielectric layers in which the dielectric layer can be formed with a uniform composition and global planarity using CMP.
These and other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.